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DDR_SDRAM_controller
- DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides t
vhdl_miaobiao
- 用vhdl实现秒表的功能，具有秒表功能,有分、秒显示，后期可以自己添加闹钟的模块。 -Use VHDL to achieve the functions of a stopwatch with a stopwatch function, who, seconds indicates that the latter can add their own alarm clock module.
timer
- vhdl代码：电子时钟VHDL程序与仿真！初学fpga者可以参考参考！！比较简单-VHDL code: electronic clock and simulation of VHDL procedures! FPGA beginner who can refer to reference! ! Relatively simple
ssz
- 数字钟，用VHDL写的各个模块，顶层用图形编辑，在实验箱上完全通过-Digital clock, using VHDL written by various modules, top-level graphics editing, in the experimental box completely through
Myshizhong
- 多功能数字时钟设计方案及电路图，以及必要分析-Multi-functional digital clock and circuit design, as well as the need to analyze the
RS232_pro
- RS232 verilog coding 全参数化设计 可以自己设定波特率 时钟频率等 完全FPGA实现调通-RS232 verilog coding the entire parametric design can set the baud rate clock frequency of FPGA to achieve complete transfer pass
clock
- 电子闹钟 clk： 标准时钟信号，本例中，其频率为4Hz； clk_1k： 产生闹铃音、报时音的时钟信号，本例中其频率为1024Hz； mode： 功能控制信号； 为0：计时功能； 为1：闹钟功能； 为2：手动校时功能； turn： 接按键，在手动校时功能时，选择是调整小时，还是分钟； 若长时间按住该键，还可使秒信号清零，用于精确调时； change： 接按键，手动调整时，每按一次，计数器加1； 如果长按，则连续快速加1，用于快速调时和定时； hour,
shizhong
- 简单的VB时钟控件操作，对于刚学习VB.net的人很有帮助-VB simple clock control operation, for people just learning VB.net helpful
VHDL
- 数字钟的设计，有时，分，秒，置数等功能。-Digital clock design, sometimes, minutes and seconds, buy a few functions.
shizhong
- 这个VHDL与其他上传的代码不同，这个代码更适合于初学者。电子时钟已经在硬件上得到成功仿真。-From the VHDL code with other different, the code is more suitable for beginners. Electronic clock has been successful in the hardware simulation.
workhard
- 数字钟 可实现正常计数校准 还有方电台报时功能 四低一高 闹钟功能-Digital clock can be calibrated to achieve a normal count timekeeping function of the radio side there are four low and one high alarm
timer
- VHDL语言设计的数字钟 具有时分秒三段显示-VHDL language designed with time-accurate digital clock shows three paragraphs
digital_clk
- 此程序是实现数字钟的，包括校时 闹钟 二十四小时和十二小时的转换-This procedure is to achieve digital clock, including the school alarm clock 24 hours and 12 hours the conversion
uart
- 串口通讯rs232,时钟频率为40Mhz,波特率为19200,没有奇偶校验,在xilinx XC3S200A板子上验证过.-Serial communication rs232, clock frequency of 40Mhz, the baud rate to 19200, no parity, in the board on xilinx XC3S200A verified.
clock
- 数字系统设计报告，多功能电子钟，显示年月日星期时分秒，及校时等功能-Digital system design report, multi-functional electronic bell, show date when the minutes and seconds a week, and school functions when
filter
- 时钟滤波器设计，可进行毛刺去除，有需要可依进行参考设计-Clock filter design can be carried out burr removed, there is a need-based reference design
EDA
- 基于VHDL语言，用Top_Down的思想进行设计的数字钟。-Based on the VHDL language, using design thinking Top_Down the digital clock.
clock
- 这是一个用VHDL语言编写的数字电路程序，仅供学习参考。-This is a language with VHDL digital circuit procedures, only to learn the reference.
VHDL
- VHDL----语言仿真闹钟设计-Simulation language VHDL---- Alarm Clock Design
Digital_Clock_VHDL
- 使用VHDL开发的简易数字时钟软件，可以作为初学者熟悉定时器应用的实例程序。-Use VHDL to develop a simple digital clock software can be used as timers for beginners familiar with examples of the application process.